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zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 1 of 13 member of the family applications ? low voltage, high density systems with intermediate bus architectures (iba) ? point-of-load regulators for high performance dsp, fpga, asic, and microprocessor applications ? industrial computing, servers, and storage ? broadband, networking, optical, and wireless communications systems ? active memory bus terminators benefits ? integrates digital power conversion with intelligent power management ? eliminates the need for external power management components and communication bus ? completely programmable via pin strapping and one external resistor ? one part that covers all applications ? reduces board space, system cost and complexity, and time to market features ? rohs lead free and lead-solder-exempt products are available ? wide input voltage range: 8v?14v ? high continuous output current: 10a ? wide programmable output voltage range: 0.5v?5.5v ? output voltage margining ? overcurrent and overte mperature protections ? overvoltage and undervoltage protections, and power good signal tracking the output voltage setpoint ? tracking during turn-on and turn-off with guaranteed slew rates ? sequenced and cascaded modes of operation ? single-wire line for frequency synchronization between multiple pols ? programmable feedback loop compensation ? enable control ? flexible fault management and propagation ? start-up into the load pre-biased up to 100% ? current sink capability ? industry standard size through-hole single-in-line package: 1.2?x0.26? ? low height of 0.84? ? wide operating temperature range: 0 to 70oc ? ul60950 recognized, csa c22.2 no. 60950-00 certified, and tuv en60950-1:2001 certified (pending) description power-one?s point-of-load converters are recommended for use with regulated bus converters in an intermediate bus architecture (iba). the zy2110 is an intelligent, fully programmable step-dow n point-of-load dc-dc module integrating digital power conversi on and power management. the zy2110 completely eliminates the need for external components for sequencing, trac king, protection, monitoring, and repo rting. performance parameters of the zy2110 are programmable by pin strapping and an exte rnal resistor and can be changed by the user at any time during product development and servic e without a need for a communication bus. reference documents no-bus tm pol converters. application note z-one ? pol converters. eutectic solder process application note z-one ? pol converters. lead-free process application note
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 2 of 13 1. ordering information zy 21 10 y ? zz product family: z-one module series: no-bus pol converter output current: 10a rohs compliance: no suffix - rohs compliant with pb solder exemption 1 g - rohs compliant for all six substances dash packaging option 2 : r1 ? 48 pcs tray q1 ? 1 pc sample for evaluation only ______________________________________ 1 the solder exemption refers to all the restricted materials exc ept lead in solder. these materials are cadmium (cd), hexavalen t chromium (cr6+), mercury (hg), polybrominated biphenyls (pbb), polybromi nated diphenylethers (pbde), and lead (pb) used anywhere except in solder. 2 packaging option is used only for orde ring and not included in the part number printed on the pol converter label. example: zy2110g-r3 : a 48-piece tray of rohs compliant pol converters. each pol converter is labeled zy2110g. 2. absolute maximum ratings stresses in excess of the absolute maximum ratings ma y cause performance degradation, adversely affect long- term reliability, and cause permanent damage to the pol converter. parameter conditions/description min max units operating temperature controller case temperature -40 105 ? c input voltage 250ms transient 15 vdc 3. environmental and mechanical specifications parameter conditions/description min nom max units ambient temperature range 0 70 ? c storage temperature (ts) -55 125 ? c weight 6 grams operating vibration (sinusoidal) frequency range magnitude sweep rate repetitions in each axis (min-max-min sweep) 5 0.5 1 2 500 hz g oct/min sweeps non-operating shock (half sine) acceleration duration number of shocks in each axis 50 11 10 g ms mtbf calculated per telcordia technologies sr-332 tbd mhrs peak reflow temperature zy2110 220 ? c peak reflow temperature zy2110g 245 260 ? c lead plating zy2110 and zy2110g 100% matte tin moisture sensitivity level jedec j-std-020c 3
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 3 of 13 4. electrical specifications specifications apply at the input voltage from 8v to 14 v, output load from 0 to 10a, ambient temperature from 0c to 70c, output capacitance consisting of 3x22 ? f ceramics and a 47 ? f tantalum, and the cca=1 unless otherwise noted. 4.1 input specifications parameter conditions/description min nom max units input voltage (v in ) 8 14 vdc undervoltage lockout threshold ramping up ramping down 7.0 6.7 vdc vdc input current v in =12v, pol is off 21 madc maximum input current v in =8v, v out =5.5v 7.5 adc 4.2 output specifications parameter conditions/description min nom max units output current (i out ) v in min to v in max -10 1 10 adc output voltage range (v out ) programmable with a resistor between trim and margin pins default (no resistor) 0.5 0.5 5.5 vdc vdc output voltage setpoint accuracy 2 v in =12v, i out =0.5*i out max , room temperature 1.5% or 20mv whichever is greater %v out line regulation 2 v in min to v in max 0.5 %v out load regulation 2 0 to i out max 0.5 %v out dynamic regulation peak deviation settling time 50% ? 100% ? 50% load step, slew rate 2.5a/ ? s, to 10% of peak deviation 240 40 mv ? s output voltage peak-to-peak ripple and noise bw=20mhz full load v in =12v, v out 1.0v v in =12v, v out =2.5v v in =12v, v out =5.0v 20 25 35 mv mv mv efficiency v in =12v full load room temperature v out =0.5v v out =0.75v v out =1.0v v out =2.5v v out =5.0v 63.0 71.1 75.9 86.4 91.3 % % % % % temperature coefficient v in =12v, i out =0.5*i out max , v out =5v 20 ppm/c switching frequency 450 500 550 khz 1 at the negative output current (bus terminator mode) efficienc y of the zy2110 degrades resulting in increased internal power di ssipation. therefore maximum allowable negative current under specific cond itions is 20% lower than the current determined from the derati ng curves shown in paragraph 5.5 2 digital pwm has an inherent quantization uncer tainty of 6.25mv that is not included in the specified static regulation paramet ers.
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 4 of 13 4.3 protection specifications parameter conditions/description min nom max units output overcurrent protection type non-latching, 130ms period threshold 155 %i out threshold accuracy -25 25 %i ocp.set output overvoltage protection type latching threshold follows the output voltage setpoint 130 1 %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v ovp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s output undervoltage protection type non-latching, 130ms period threshold follows the output voltage setpoint 75 %v o.set threshold accuracy measured at v o.set =2.5v -2 2 %v uvp.set delay from instant when threshold is exceeded until the turn-off command is generated 6 s overtemperature protection type non-latching, 130ms period turn off threshold temperature is increasing 120 ? c turn on threshold temperature is decreasing after module was shut down by otp 110 ? c threshold accuracy -5 5 ? c delay from instant when threshold is exceeded until the turn-off command is generated 6 s power good signal (pgood pin) logic v out is inside the pg window and stable v out is outside of the pg window or ramping up/down high low n/a lower threshold follows the output voltage setpoint 90 %v o.set upper threshold follows the output voltage setpoint 110 %v o.set delay from instant when threshold is exceeded until status of pg pin changes 6 s threshold accuracy measured at v o.set =2.5v -2 2 %v o.set ___________________ 1 minimum ovp threshold is 1.0v
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 5 of 13 4.4 feature specifications parameter conditions/description min nom max units tracking rising slew rate proportional to sync frequency 0.1 v/ms falling slew rate proportional to sync frequency -0.5 v/ms enable (en pin) en pin polarity positive (enables the output when en pin is open or pulled high) en high threshold 2.3 vdc en low threshold 1.0 vdc open circuit voltage 3.3 vdc turn-on delay from en pin changing state to v out starting to ramp up 0 ms turn-off delay from en pin changing state to v out reaching 0v 11 ms feedback loop compensation (cca pin) cca pin is open recommended c out /esr range, combination of ceramic + tantalum 50/5 + 220/40 100/5 + 470/40 400/5 + 2000/20 f/m ? f/m ? cca pin is connected to gnd recommended c out /esr range, ceramic 100/5 220/5 400/5 f/m ?
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 6 of 13 4.5 signal specifications parameter conditions/description min nom max units vdd internal supply voltage 3.15 3.3 3.45 v sync line vil_s low level input voltage -0.5 0.3 x vdd v vih_s high level input voltage 0.75 x vdd vdd + 0.5 v vhyst_s hysteresis of input schmitt trigger 0.25 x vdd 0.45 x vdd v iol_s low level sink current v(sync)=0.5v 14 60 ma ipu_s pull-up current source v(sync)=0v 300 1000 a tr_s maximum allowed rise time 10/90%vdd 300 ns cnode_s added node capacitance 5 10 pf freq_s clock frequency of external sync line 475 525 khz tsynq sync pulse duration 22 28 % of clock cycle t0 data=0 pulse duration 72 78 % of clock cycle inputs: cca, en, im iup_x pull-up current source v(x)=0 25 110 a vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v rdnl_x external pull down resistance pin forced low 10 k ? power good and ok inputs/outputs iup_pg pull-up current source v(pg)=0 25 110 a iup_ok pull-up current source v(ok)=0 175 725 a vil_x low level input voltage -0.5 0.3 x vdd v vih_x high level input voltage 0.7 x vdd vdd+0.5 v vhyst_x hysteresis of input schmitt trigger 0.1 x vdd 0.3 x vdd v iol_x low level sink current at 0.5v 4 20 ma
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 7 of 13 5. typical performance characteristics 5.1 efficiency curves 65 70 75 80 85 90 95 012345678910 output current, a efficiency, % vo=5.0v vo=3.3v vo=2.5v vo=1.8v vo=1.2v figure 1. efficiency vs. load. vin=9.6v 60 65 70 75 80 85 90 95 012345678910 output current, a efficiency, % vo=5v vo=3.3v vo=2.5v vo=1.8v vo=1.2v figure 2. efficiency vs. load. vin=12v 65 70 75 80 85 90 95 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 output voltage, v efficiency, % vin=12v vin=9.6v figure 3. efficiency vs. output voltage, iout=10a 75 80 85 90 95 8 9 10 11 12 13 14 input voltage, v efficiency, % vo=1.2v vo=2.5v vo=5v figure 4. efficiency vs. input voltage. iout=10a
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 8 of 13 5.2 turn-on characteristics figure 5. tracking turn-on. vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 5.3 turn-off characteristics figure 6. tracking turn-off vin=12v, ch1 ? v1, ch2 ? v2, ch3 ? v3 5.4 transient response the pictures below show the deviation of the output voltage in response to t he 50%-100%-50% step load at 2.5a/ s. in all tests the pol converter had a total of 110 f ceramic and tantalum capacitors connected across the output pins. the speed of the transient response was varied by selecting different cca settings. figure 7. vin=12v, vout=5v. cca=0 figure 8. vin=12v, vout=5v. cca=1
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 9 of 13 figure 9. vin=12v, vout=1v. cca=0 figure 10. vin=12v, vout=1v. cca=1 5.5 thermal derating curve 3 4 5 6 7 8 9 10 25 35 45 55 65 75 ambient temperature, c load current, a 0 lfm 100 lfm (0.5 m/s) 200 lfm (1 m/s) 300 lfm (1.5 m/s) 400 lfm (2 m/s) 500 lfm (2.5 m/s) figure 11. thermal derating curves. vin=12v, vout=5v
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 10 of 13 6. typical application pol2 22uf trim margin im cca en sync ok pgood 4.7uf pol3 22uf trim margin im cca en sync ok pgood 4.7uf pol1 22uf 47uf vin vout gnd trim margin im cca en sync ok pgood 4.7uf 22uf ibv vo1 vo2 vo3 enable vin vin vout pgnd vout gnd 22uf 22uf 47uf 22uf 22uf 22uf 47uf 22uf 22uf 22uf figure 12. complete schematic of application with three independent outputs. intermediate bus voltage is from 8v to 14v. in this application four pol converters are configur ed to deliver three independent output voltages. output voltages are programmed with the resistors connected bet ween trim and margin pins of individual converters. pol1 is configured as a master (im pin is grounded) and all other pol converters are synchronized to the switching frequency of pol1. all converters are controlled by the common enable signal . turn-on and turn-off processes of the system are illustrated by pictures in figure 5 and figure 6.
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 11 of 13 7. pin assignments and description pin name pin number pin type buffer type pin description notes ok 8 i/o pu fault status connect to ok pin of other z- pols. leave open, if not used sync 9 i/o pu frequency synchronization line connect to sync pin of other z-pols or to an external clock generator pgood 6 i/o pu power good im 10 i pu master mode tie to gnd to make the pol the clock master or leave open to synchronize to external clock cca 2 i pu compensation coefficient address tie to pgnd for 0 or leave open for 1 margin 3 a output voltage margining to program the output voltage, connect a resistor between margin and trim en 5 i pu enable pol is on when the pin is high or floating. pol is off when the pin is low or connected to gnd trim 4 a output voltage trim to program the output voltage, connect a resistor between margin and trim vout 1 p output voltage gnd 7 p power ground vin 11 p input voltage legend: i=input, o=output, i/o=input/output, p=power, a=analog, pu=internal pull-up 8. pin and feature description 8.1 ok, fault status the open drain input/output with the internal pull-up resistor. the pol converter pulls its ok pin low, if a fault occurs. pulling low the ok input by an external circuitry turns off the pol converter. 8.2 sync, frequency synchronization line the bidirectional input/output with the internal pull-up resistor. if the pol converter is configured as a master, the sync line propagates clock to other pol converters. if the pol converter is configured as a slave, the internal clock recovery circuit synchronizes to the cl ock of the sync line. 8.3 im, interleave mode the input with the internal pull-up resistor. pulling the im pin low configures a pol converter as a master. 8.4 pg, power good the open drain input/output with the internal pull-up resistor. the pin is pulled low by the pol converter, if the output voltage is outside of the window defined by the power good high and low thresholds. 8.5 cca, compensation coefficient address the input with internal pull-up to select one of 2 sets of digital filter coefficients optimized for different characteristics of output capacitance. 8.6 margin, output voltage margining the output of the 2v internal voltage reference that is used to program the output voltage of the pol converter. 8.7 en, enable the input with the internal pull-up resistor. the pol converter is turned off, when the pin is pulled low 8.8 trim, output voltage trim the input of the trim comparator for the output voltage programming. the output voltage can be programmed by a single resistor connected between margin and trim pins.
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 12 of 13 9. application information 9.1 output voltage programming resistance of the trim resistor is determined from the equation below: , ) 5 . 5 ( 20 out out trim v v r ? ? ? k ? where v out is the desired output voltage in volts. if the r trim is open or the trim pin is shorted to pgnd, the v out =0.5v. 9.2 output voltage margining margining can be implemented by changing the resistance between the ref and trim pins. figure 13. margining configuration in the schematic shown in figure 13, the nominal output voltage is set with the trim resistor r trim calculated from the equation in the paragraph 9.1. resistors r up and r down are added to margin the output voltage up and down respectively and determined from the equations below. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? % % 5 20 20 v v r r r r trim trim trim up , k ? ?? ? ? ? ? ? ? ? ? ? ? ? ? % 100 % 20 v v r r trim down , k ? where r trim is the value of the trim resistor in k ? and v% is the absolute value of desired margining expressed in percents of t he nominal output voltage. during normal operation the resistors are removed from the circuit by the switches. the ?margining down? switch is normally closed shorting the resistor r down while the ?margining up? switch is normally open disconnecting the resistor r up . an alternative configuration of the margining circuit is shown in figure 14. in the configuration both switches are normally open that may be advantageous in some implementations. figure 14. alternative margining configuration r up and r down for this configuration are determined from the following equations: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? % % 5 20 20 v v r r r r trim trim trim up , k ? ? ? ? ? ? ? ? ? ? ? ? ? ? % % 100 20 20 v v r r r trim trim down , k ? caution : noise injected into the trim node may affect accuracy of the output voltage and stability of the pol converter. always minimize the pcb trace length from the trim pin to external components to avoid noise pickup. refer to no-bus tm pol converters. application note on www.power-one.com for more application information on this and other product features. margin trim pol gnd r down r trim margining down switch (normally closed) margining up switch (normally open) r up margin trim pol gnd r trim r down margining down switch (normally open) margining up switch (normally open) r up
zy2110 10a no-bus pol data sheet 8v to 14v input ? 0.5v to 5.5v output zd-02013 rev. bb.2, 30-jun-10 www.power-one.com page 13 of 13 10. mechanical drawings all dimensions are in mm tolerances: xx.x: ? 0.1 xx.xx: ? 0.05 figure 15. mechanical drawing figure 16. recommended footprint ? top view notes: 1. nuclear and medical applications - power-one products are not designed, intended for use in, or authorized for use as critic al components in life support systems, equipment used in hazardous envi ronments, or nuclear control systems without the express wr itten consent of the respecti ve divisional president of power-one, inc. 2. technical revisions - the appearance of products, including safety agency certifications pictured on labels, may change depe nding on the date manufactured. specifications are subject to change without notice.

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